Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /LPSPI /SPI_CTRLR1

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Interpret as SPI_CTRLR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NDF

Description

Control Register 1

Fields

NDF

Number of Data Frames. When the SPI_CTRLR0[TMOD] = 0x2 or SPI_CTRLR0[TMOD] = 0x3, this bit field sets the number of data frames to be continuously received by the SPI. The SPI continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables the user to receive up to 64KB of data in a continuous transfer. When the SPI is configured as a serial slave, the transfer continues for as long as the slave is selected. Therefore, this bit field serves no purpose and is not present when the SPI is configured as a serial slave.

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